Publications

A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing

Published in Int. Symposium on VLSI Circuits (VLSI Circuits), 2023

Abstract: This work presents the world’s first post-quantum hybrid crypto SoC that achieves an 800Mpbs throughput and consumes only 4. 8mW for remote neural interfacing. The chip dissipates 0.70μJ/OP for the handshake and 48pJ/B for data encryption in 40nm CMOS. Flexible authenticated encryption is supported. This work achieves 3-175x higher area efficiency with 16-41x less energy than state-of-the-art designs.

Recommended citation: L.-H. Lin, Z.-S. Fu, P.-S. Chen, B.-Y. Yang, and C.-H. Yang, "A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing," Int. Symposium on VLSI Circuits (VLSI Circuits), June 2023.

A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring

Published in IEEE Asian Solid-State Circuits Conference (A-SSCC), 2021

Recommended citation: P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, "A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring," IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.