Curriculum Vitae

Research Interest

Energy efficient hardware accelerator for digital signal processing

Ph.D. in Electrical and Computer Engineering, University of Michigan, Present
M.S. in Electronics Engineering, National Taiwan University, 2021
- Thesis: An Energy-Efficient Accelerator IC for Dark Channel Prior Based Blind Image Deblurring
- Adivsor: Prof. Chia-Hsiang Yang
B.S. in Electrical Engineering, National Taiwan University, 2018

Journal Paper
- P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, “A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring,” IEEE Journal Solid-State Circuits (JSSC), vol. 59, no. 6, pp. 1899-1911, June 2024.
Conference Papers
- E. Dikopoulos, L. Wormald, Y.-T. Hsu, W. Tang, P.-S. Chen, Z. Zhang, M. P. Flynn, “A Relaxation Oscillator-Based Probabilistic Combinatorial Optimization Engine for Soft Decoding of LDPC Codes,” IEEE European Solid-State Electronics Research Conference (ESSERC), Sep. 2024.
- L.-H. Lin, Z.-S. Fu, P.-S. Chen, B.-Y. Yang, and C.-H. Yang, “A 4.8mW, 800Mbps Hybrid Crypto SoC for Post-Quantum Secure Neural Interfacing,” Int. Symposium on VLSI Circuits (VLSI Circuits), June 2023.
- P.-S. Chen, Y.-L. Chen, Y.-C. Lee, Z.-S. Fu, C.-H. Yang, “A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.

Research Assistant, Digital Circuits and Systems Lab, NTU, Aug. 2021 - Present
Mandatory Military Service, R.O.C. Army, Apr. 2021 - July 2021
Graduate Student Researcher, Digital Circuits and Systems Lab, NTU, July 2018 - Mar. 2021
- Advisor: Prof. Chia-Hsiang Yang
- Project: Blind image deblurring accelerator IC
Undergraduate Student Researcher, Digital Circuits and Systems Lab, NTU, Mar. 2018 - June 2021
Electrical Engineering Intern, HP Inc., July 2017 - July 2018

Programming Language: Verilog, MATLAB, Python, C/C++, Latex
Hardware Design Tools: NC-verilog, Verdi/nWave, Design Compiler, Innovus, Calibre, Altera Quartus